Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly to a sealing structure for a bonded wafer and a method of forming the sealing structure. Specifically, the sealing structure can be used on the bonded wafer during C-mode Scanning Acoustic Microscope (C-SAM) analysis of the bonded wafer.
Description of the Related Art
In the field of consumer electronics, multifunction devices are becoming more and more popular with consumers compared to simple function devices. However, the manufacturing process for multifunction devices is usually more complex. For example, numerous chips having different capabilities may need to be integrated onto a circuit board in a multifunction device. Recently, 3D integrated circuit (3D-IC) technology has been developed to integrate the different chips onto the circuit board. A 3D-IC is a type of system-level integrated structure in which the chips are stacked in a vertical plane direction to save space. The number of pins on an edge portion of each chip can be configured depending on device needs. The chips can be connected to one another using wirebonds.
However, the current 3D-IC technology has some deficiencies. For example, as the number of stacked chips increases, it becomes more difficult to connect the different chips together due to space constraints. Also, more gold wire may be needed for the wirebonds, which increases packaging costs. Furthermore, the layout of the wirebonds may be complicated since some wirebonds may crisscross in order to connect the different chips. To avoid shorting the wirebonds, the spacing between the wirebonds may increase, but this could increase the form factor of the device.
In addition to traditional wirebonds, 3D-IC technology may also include the use of through silicon vias (TSVs). For example, different chips (such as processor chips, field programmable gate array (FPGA) chips, memory chips, radio frequency (RF) chips, optical chips, etc.) undergo thinning and are then bonded together and interconnected using TSVs. In particular, the wafer/chip bonding, the use of TSVs and interposers, coupled with other packaging techniques, can allow a large number of chips to be stacked and interconnected within a limited area.
Wafer level bonding (e.g. wafer level Cu—Cu bonding) is a key technology in 3D-ICs. In particular, there is a need for real-time detection of the wafer bonding quality and yield.
In recent years, ultrasonic scanning microscopy (e.g., C-SAM) has been successfully used in the electronics industry, especially in packaging research and experimental laboratories. Ultrasound provides non-destructive testing capabilities without the need to remove the external packaging of the components. For example, C-SAM can be used to effectively detect damage to the IC packaging due to moisture or heat. The damage may include interfacial delamination, air gaps, cracks, etc. When ultrasound passes through different mediums, echoes will be produced in regions having different material densities and coefficients of elasticity. The echo intensity will vary depending on the different material densities and coefficients of elasticity, and the aforementioned feature enables C-SAM to detect defects within the materials. The defects can be imaged based on the echo signals received by the C-SAM. As a result, the presence, size, and location of defects (for example, interfacial delamination, air gaps, or cracks in the IC chip/package that is being tested) can be determined from images produced by the C-SAM.
The bonding quality of a eutectic bond can be inspected using C-SAM. A eutectic bond may be formed at the interface between two wafers when the two wafers are bonded together. FIG. 1 depicts a schematic cross-sectional view of a bonded wafer according to the prior art. Referring to FIG. 1, when a first wafer 101 and a second wafer 102 are bonded together, a gap 10 is formed at the edge of the bonded wafer. In a C-SAM tool, the IC chip/package that is to be imaged is usually placed in a container of water, and ultrasonic waves are transmitted through the water and passes through the IC chip/package. As previously mentioned, defects can be imaged based on the echo signals received by the C-SAM tool. However, when the bonded wafer is placed into the C-SAM tool, water (in the container) may flow into the gap 10 and air bubbles within the gap 10 could distort the CSAM imaging results.
To mitigate the above problem, superglue is usually applied to the edge of the bonded wafer, to prevent water from flowing into the gap 10 at the edge of the bonded wafer and creating air bubbles. FIG. 2 illustrates C-SAM images of a bonded wafer whereby superglue has been applied to the edge of the bonded wafer according to the prior art. The image on the right of FIG. 2 is a magnified view of the circled region in the image on the left of FIG. 2. By using the superglue, relatively clear C-SAM images can be produced in the bulk area (center region) of the bonded wafer. However, the application of the superglue could damage the bonded wafer, especially at the edge of the bonded wafer which is more prone to stress cracks. In addition, a superglue region 20 is formed on the periphery of the bonded wafer, and it is extremely difficult to remove the superglue from the bonded wafer.